ASML, TSMC, and Imec demonstrated a scalable 300mm manufacturing process for 2D material transistors. The partners presented the development at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits. The process successfully produced both nFETs and pFETs at a 50nm pitch.
The integration scheme utilizes EUV lithography and a novel transistor architecture. This approach enabled channel lengths as small as 28nm. The manufacturing process achieved a high operational yield of 94 percent.
This advancement facilitates the industrial adoption of post-silicon logic devices. It addresses the challenge of translating laboratory concepts into mass-producible processes. The breakthrough reinforces ASML’s leadership in next-generation semiconductor technology.