TSMC is evaluating its next-generation CoPoS (Chip-on-Panel-on-Substrate) packaging technology on a pilot line. The company is running a dual-track test using equipment from both global and Taiwanese domestic suppliers. This initiative aims to build a competitive ecosystem for future AI chips as the company looks beyond its current CoWoS technology.
In a separate move, TSMC partnered with research hub Imec and equipment giant ASML to develop transistors using 2D materials. The collaboration utilizes a scalable 12-inch wafer platform to move next-generation transistor technology into high-volume manufacturing. This research aims to produce smaller, more powerful chips for future hardware.