Taiwan Semiconductor Manufacturing Co. (TSMC) is accelerating development of next-generation panel-level packaging. This technology enables more powerful and efficient AI processors. The company currently operates a Chip-on-Panel-on-Substrate (CoPoS) pilot line. This dual-track evaluation tests equipment from both global vendors and local Taiwanese suppliers.
The initiative signals an intensifying race for advanced packaging leadership beyond the current CoWoS standard. Panel-level packaging supports larger and more complex chip integrations for AI data centers. TSMC is pitting international firms like Applied Materials against local contenders. The evaluation focuses on process stability, cost-efficiency, and local support.
TSMC anticipates reaching mass production within the next two to three years. These steps directly impact the roadmaps of major AI chip designers. The shift will influence the entire global semiconductor supply chain.