Samsung Electronics has officially integrated wafer-to-wafer hybrid bonding into its next-generation DRAM roadmap. The company reclassified the process from a research project named B1b to the official D0a designation. This technology will serve as the baseline for Samsung’s first sub-10-nanometer DRAM generation.
Hybrid bonding manufactures memory cells and peripheral circuits on separate wafers before bonding them directly. This method increases chip density and improves overall performance. Samsung reclassified its previous D0a technology, vertical-channel-transistors (VCT), as a separate derivative called D0a-V.
The strategic shift aims to bypass technical and commercialization hurdles currently facing VCT DRAM. Industry sources expect these hybrid-bonded chips to reach commercial readiness in approximately two years. Samsung is also evaluating this technology for its future HBM5 high-bandwidth memory products.